1. Field of the Invention
The present invention relates to electronically controlled delay circuits, and more particularly to high-speed voltage-controlled delay locked loops. The invention can be used to generate a swept-delay clock for sampling-type radar, TDR and laser receivers.
2. Description of Related Art
High range resolution pulse-echo systems such as wideband pulsed radar, pulsed laser rangefinders, and time domain reflectometers often sweep a timing circuit across a range of delays. The timing circuit controls a receiver sampling gate such that when an echo signal coincides with the temporal location of the sampling gate, a sampled echo signal is obtained. The range of the sampled echo is directly determined from the timing circuit, so highly accurate timing is needed to obtain high accuracy range information.
Timing circuits are implemented with both open loop and closed loop control architectures. Open loop timing circuits often use an analog voltage ramp to drive a comparator, with a comparator reference voltage controlling the delay. Open loop circuits are subject to component and temperature variations, and are not very accurate due to the difficulty in generating a precision voltage ramp with sub-nanosecond accuracy.
Closed loop timing circuits are generally a variation on a phase-locked loop (PLL)--the delay locked loop (DLL). The difference between a PLL and a DLL is often a matter of definition--the DLL controls the relative delay between two digital waveforms, which can also be considered to be relative phase. In the present invention, the primary attribute of interest is the time difference between the two waveforms, so the term DLL is appropriate.
DLL circuits are often used to control clock skew on LSI chips, or to generate multi-phase clocks for digital computing applications. Generally, digital computer clock circuits do not need the sub-10 ps accuracy required of radar and laser rangefinders with 1-mm range accuracy. Thus, most prior art circuits do not address the accuracy needed for the intended applications of the present invention.
A prior art DLL circuit operates by 1) comparing the phase of two clock waveforms using a phase comparator, such as an X-OR gate, 2) integrating the phase comparator output to obtain a DC voltage indicative of the phase difference between the two clocks, and 3) applying the DC voltage to an amplifier whose output controls the phase shift or time delay through one of the clock paths.
All known PLL and DLL circuits employ phase comparators, which limit the accuracy of the entire circuit. A particular problem with phase comparators using digital gates is edge crosstalk between the two input clocks. Edge crosstalk typically occurs in the 0 and 180 degree regions and can produce an error of 0.1 nanoseconds or more, depending on edge speeds and coupling factors. Another major error occurs when the comparator output is a digital pulse of diminishing width--the comparator output cannot produce a 0-ns wide pulse at its output. Further, digital phase comparators can introduce temporal error due to gate propagation delay changes, and inaccuracies due to pulse ringing and other aberrations. It is very difficult to obtain delay accuracies in the range of 1-10 picoseconds due to phase comparator limitations.
A "Precision Digital Pulse Phase Generator" is disclosed by McEwan in U.S. Pat. No. 5,563,605 which employs a 1-micron NAND gate as a phase comparator in a DLL configuration. The NAND gate must operate with at least 4-ns of clock timing difference to allow for the propagation of a 4-ns or wider pulse through it. This presents a problem for radar circuits that must operate down to zero range, such as for fluid level measurement in a tank, since the 4-ns minimum delay represents 66 cm minimum radar range. Furthermore, the accuracy of the NAND gate phase comparator is highly suspect, since the NAND gate has a 2-ns propagation delay, which is 1000.times. higher than the desired circuit accuracy of .about.2 ps.
The present invention significantly advances the accuracy of DLL circuits by eliminating the phase comparator altogether.